(a) Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device with triple gate insulating layers.
(b) Description of the Related Art
Generally, a Metal Oxide Silicon (MOS) transistor has a gate insulating layer formed on a semiconductor substrate, a gate formed on the gate insulating layer, and source and drain regions formed within the substrate. Various manufacturing methods of this transistor are disclosed in U.S. Pat. Nos. 6,204,137, 6,365,450, 6,406,945, 6,515,338 and 6,544,827.
Recently, to satisfy requirements of variously manufactured goods, a technique for forming devices to be applied for several objectives in one chip has been researched.
In this technique, as gate voltages of MOS transistors applied to the devices are different from each other, gate insulating layers must be formed with different thicknesses in each of the devices.
For example, in the case a high voltage device, a middle voltage device and a low voltage device are formed in one chip, triple gate insulating layers having different from thickness from each other are employed. More specifically, a first gate insulating layer of a first thickness to be relatively thick is formed at the high voltage device region, a second gate insulating layer of a second thickness to be thinner than the first thickness is formed at the middle voltage device region, and a third gate insulating layer of a third thickness to be thinner than the second thickness is formed at the low voltage device region.
Therefore, to obtain good properties corresponding to each of the devices, it is important that thicknesses and good qualities of gate insulating layers being opportune to each of the devices are obtained.